module top(clock,rst,dig[2:0],seg[7:0]);
input clock,rst;
output [2:0] dig;
output [7:0] seg;
wire [7:0] out;
wire clk_out1,clk_out2;
div1 u1(clock,rst,clk_out1);
div2 u2(clock,rst,clk_out2);
counter u3(clk_out1,out[7:0]);
smg2 u4(rst,clk_out2,out[7:0],dig[2:0],seg[7:0]);

endmodule